Electrostatic discharge (ESD) can damage devices fabricated on integrated circuit (IC) chips, causing performance degradation or failures. Consequently, one of many considerations for IC design is on-chip ESD protection. However, due to the ever-increasing requirements for higher speeds, smaller devices and product reliability, the significance of on-chip ESD protection has now become critical in IC design.
An on-chip ESD protection circuit of interest is an RC-triggered ESD power clamp circuit. A conventional RC-triggered power clamp circuit includes an N-channel metal oxide semiconductor (NMOS) clamping transistor, an inverter (or inverter chain) and an RC circuit. The NMOS clamping transistor is connected between a VDD rail and a VSS rail. The RC circuit is also connected between the VDD rail and the VSS rail. The RC circuit comprises a resistive element and a capacitor, which are connected in series between the VDD rail and the VSS rail. The resistive element can be an NMOS or P-channel metal oxide semiconductor (PMOS) transistor. The output of the inverter is connected to the gate of the NMOS clamping transistor and the input of the inverter is connected to the output of the RC circuit at a node between the resistive element and the capacitor.
The rise time of VDD during power-up under normal operation is in millisecond range. Since this rise time of VDD is longer than the RC delay of the RC delay circuit, the output of RC circuit is at the same potential as the VDD power rail, and thus, the NMOS clamping transistor is not turned on and remains in the off state. However, when a positive ESD, whose rise time is in sub-micro second range, appears on the VDD rail, the RC circuit and the inverter operate to turn on the NMOS clamping transistor to route the ESD to the VSS rail through the NMOS clamping transistor to prevent the ESD from reaching the downstream devices. After the ESD event, the NMOS clamping transistor is again turned off so that normal operations may continue.
A concern with the conventional RC-triggered power clamp circuit is that false triggering of the NMOS clamping transistor may occur during normal operations when either voltage overshoot occurs on the VDD rail or VDD power-up rise time is extremely fast (μs range). Another concern with the conventional RC-triggered power clamp circuit is that the RC time constant is relatively short. Longer RC time constant is desired for such an ESD protection circuit since it provides more time to discharge ESD through the NMOS clamping transistor. Longer RC time constant can be achieved by increasing the capacitor size. However, such a large capacitor requires a significant amount of valuable chip real estate, which makes this RC triggered circuit based ESD solution impractical.
In view of these concerns, there is a need for an RC-triggered power clamp circuit and method for providing ESD protection with reduced false triggering and increased RC time constant.